All automatic test generation programs that are known to the inventor require some type of defect model. The defect model is used to identify test stimulus patterns for detecting the modelled defects. The defect model is also employed to ascertain the effectiveness of the generated test stimulus patterns in detecting the defects.
Traditionally a "stuck-at" fault model has been used in the test industry. That is, a defect is modelled as a node or pin that is shorted to (stuck-at) another node or pin, such as a logic one level or a logic zero level. More recently, a transition fault model has been used to model dynamic defects that require a sequence of two test stimulus patterns to excite the defect.
Both of these fault models place the faults on the input and output pins of gate level primitives. The gate level primitives are employed to model the circuit or integrated circuit to be tested. For example, a complex circuit can be modelled as a number of constituent gate level primitives including AND, OR and inverter gates. Furthermore, assemblages of such gates are used to model higher level logic functions, such as various types of latches and multiplexers (MUXes), which are then stored within a library of higher level logic functions. A particular higher level logic function, such as a D-type FF or a two-input MUX, may be referenced a number of times within a given circuit design.
One problem associated with the gate level model is that it becomes difficult to support some higher level primitives, such as latches and XOR gates, due to an uncertainty as to how these primitives may have been actually implemented by the manufacturer. If only a pin fault model is assumed, certain defects that are internal to these higher level primitives may go un-modelled and therefore undetected.
A further problem is presented in that, in many cases, a true circuit defect cannot be adequately represented by a pin fault on a gate. To more accurately represent such defects it is known to instead employ a lower level transistor or switch level circuit model. Although the overall accuracy of fault modeling may be improved by this approach, some accuracy problems still remain. Furthermore, the use of a transistor or switch level circuit model, as opposed to the gate level circuit model, significantly increases the complexity of the fault model, thereby increasing the required time and effort involved in test pattern generation and fault simulation.
In the past, certain faults have been modelled by inserting additional, redundant logic into the circuit model with only certain pin faults active. These active pin faults force the test generation software to produce a specific pattern necessary to excite the defect. Although this approach allows the test generation system to remain at the gate level, as opposed to the transistor level, it still increases the circuit size (because of the additional gates used to contain the special pin faults) and thus increases the effort required to perform test generation and fault simulation.
In an IBM Technical Bulletin, "Flexible Fault Model for Test Generation", vol 31, no. 2, July, 1988 pp 299-302, P. C. Shearon discloses a technique to describe a logic failure for a logic block as an "objective" in terms of the patterns required to test the logic block failure and the expected good and failure responses. However, a capability to test for faults or defects within a logic block is not provided, neither is an ability to logically associate the objectives with one another.
Commonly assigned U.S. Pat. No. 5,018,144 (Corr et al.) entitled "Logic Performance Verification and Transition Fault Detection" is referenced as being of interest for teaching an improvement in a level sensitive scan design (LSSD) test system that enables the performance of both stuck-at and transition fault testing.
U.S. Pat. No. 4,853,928 (Williams) entitled "Automatic Test Generator for Logic Devices" teaches an algebraic recursion process to solve test conditions for sequential and combinatorial logic devices. Only external pin faults are considered by this technique, and defects which may occur within a circuit, are not modelled.